Digital Logic & Computer Systems

Instructor Information

• Instructor: Dr. Tessa Becker (Associate Professor of Electrical & Computer Engineering)
• Email: tbecker@university.alkimi.ai
• Office: Rowan Engineering Center 214
• Office Hours:
  • Monday & Friday: 9:30–11:00 a.m. (In person, Rowan Engineering Center 214)
  • Wednesday: 4:00–5:00 p.m. (Virtual via Zoom; link posted in Canvas)
  • Also available by appointment.

Course Description

Number systems, Boolean algebra, combinational and sequential logic, finite state machines, and hardware description languages, with a weekly three-hour laboratory using FPGA boards. EE 210 provides a rigorous introduction to digital systems design, spanning Boolean algebra, combinational logic networks, synchronous sequential circuits, and modern hardware description languages. Students analyze and synthesize digital circuits using SystemVerilog, simulate designs using industry-standard EDA tools, and implement digital hardware on field-programmable gate array (FPGA) development boards. The course connects foundational gate-level logic with modular digital architectures including arithmetic logic units, finite state machines, and register files.

Prerequisites

CS 150.

Measurable Student Learning Outcomes

Upon successful completion of EE 210, students will be able to:

1. Analyze and Minimize Boolean Logic: Apply Boolean algebra theorems, Karnaugh maps, and algebraic factorization to minimize combinational logic functions and design optimal two-level and multi-level circuits.
2. Design Combinational Subsystems: Construct MSI combinational modules including multiplexers, decoders, priority encoders, comparators, and arithmetic circuits such as carry-lookahead adders and ALUs.
3. Synthesize Synchronous State Machines: Design, optimize, and encode Moore and Mealy finite state machines, deriving state transition diagrams, excitation tables, and next-state logic.
4. Model Hardware with SystemVerilog: Author synthesizable SystemVerilog models for combinational and sequential modules, write self-checking testbenches, and verify timing and functional correctness via simulation.
5. Implement Digital Systems on FPGAs: Program, test, and debug digital logic systems on physical FPGA development boards using switches, buttons, seven-segment displays, and serial communication interfaces.

Required Course Materials & Approximate Costs

1. Harris, David, and Sarah L. Harris. Digital Design and Computer Architecture: RISC-V Edition. Morgan Kaufmann, 2021. Approx. $75 digital rental ($95 purchase; reserve copies available in Alkimi Library).
2. FPGA Development Board (Digilent Basys 3 Artix-7) and EDA synthesis software (Vivado ML Standard). Provided in laboratory Rowan Engineering Center 150; free software download for student laptops.
3. Total estimated cost: Approx. $0 (library reserve & lab equipment) to $75 (textbook rental).

Generative AI Policy (AI Level 2: AI Permitted with Disclosure for Specified Tasks)

In accordance with Alkimi University Academic Policies (Student Handbook §5.8), EE 210 operates under AI Level 2.

• What is permitted: Students may consult AI tools to clarify SystemVerilog syntax, understand simulator compiler error diagnostics, and learn standard testbench assertion patterns.
• What is prohibited: Generative AI must not be used to author complete SystemVerilog modules for graded lab assignments, generate state machine transition logic for project deliverables, or complete examination questions. All hardware designs must be synthesized and tested independently.
• Disclosure: Whenever AI tools are consulted to resolve HDL syntax or understand simulation anomalies, students must document the interaction in their lab notebook with the exact prompt and describe how the design was physically verified on the FPGA board.

Grading Components and Weights

• Weekly Problem Sets: 10% (Due Wednesdays at 11:59 p.m. in Canvas (weeks 2–14; lowest dropped))
• Laboratory Experiments & FPGA Checkoffs: 25% (Completed during Tuesday lab sessions with checkoffs and lab reports due Sundays at 11:59 p.m. (lowest dropped))
• FPGA Digital System Design Project: 15% (Due Friday, November 20 at 11:59 p.m.)
• Midterm Exam 1 (Combinational Logic & HDLs): 15% (In class, Friday, October 2)
• Midterm Exam 2 (Sequential Logic & State Machines): 15% (In class, Friday, November 6)
• Comprehensive Final Examination: 20% (Monday, December 14, 2026, 8:00–10:00 a.m.)

Grading Scale (Alkimi University Standard)

• A: 93–100% | A-: 90–92%
• B+: 87–89% | B: 83–86% | B-: 80–82%
• C+: 77–79% | C: 73–76% | C-: 70–72%
• D+: 67–69% | D: 60–66% | F: Below 60%
• Extra credit: No extra credit assignments are offered in EE 210.

Course Schedule (Fall 2026)

Course Policies

Attendance Policy

Regular attendance at both lecture and laboratory sessions is required to master digital logic design and hardware debugging. Laboratory sessions utilize specialized FPGA hardware and benchtop oscilloscopes that cannot be replicated outside scheduled hours. If an unavoidable absence arises due to illness or approved university events, notify Dr. Becker in advance. Students who miss the first two class meetings without notifying the instructor may be dropped. Students may miss class for religious observance without penalty if they notify the instructor in writing within the first two weeks of the semester (by Wednesday, September 9, 2026). Absences for university-sponsored activities (athletics, performances, conferences) are excused with a letter from the sponsoring office at least one week in advance.

Late Work Policy

Homework problem sets submitted after the deadline incur a 15% penalty per 24 hours late, up to 48 hours. Laboratory checkoffs must be completed during the scheduled lab session or within open lab hours prior to Sunday at 11:59 p.m.; late lab reports incur 10% per day. To accommodate personal emergencies, the lowest homework score and lowest lab score will be dropped.

Final Exam Policy

The final examination (Monday, December 14, 2026, 8:00–10:00 a.m.) is scheduled by the University Registrar and can't be moved without the Dean's written approval (Faculty Handbook §5.5). A student with three or more final exams on the same calendar day may reschedule one of them. Requests go to the instructor of the middle exam by the last day of classes. For this term, send the request by Wednesday, December 9, 2026 (Student Handbook §6.4).